1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, in particular to a processing technology of an interconnect structure that includes an etching stopper formed in a dielectric film.
2. Description of the Related Art
Recently, multilayered interconnect line of semiconductor devices becomes increasingly scaled down as one of the solution to a problem such as high-speed operation, low cost manufacturing, and soon. On the other hand, interconnect delay (RC delay) problem has come to known with increasing interconnect resistance and capacitance among interconnect lines. Then, this problem becomes a major limiting factor in operation speed of devices. Consequently, some measures for solving this problem are known these days. Among those measures, using of copper as a material for interconnect lines instead of aluminum in order to reduce interconnect resistance, and using of low dielectric constant materials for dielectric films in order to reduce capacitance among interconnect lines are well known.
Since it is difficult to perform reactive ion etching on copper, the damascene process is usually employed for forming the interconnect when copper is used as the interconnect material. FIGS. 1A to 1D show an example of process of forming copper interconnects by a damascene process. There exists two types of the damascene process presently well known, one of which is a single damascene process in which an interconnect layer and a via plug are formed step-by-step, and the other of which is a dual damascene process in which an interconnect layer and a via plug are formed simultaneously (JP-A No. 2000-91425). The explanation of the latter type will be shown in the following as an example.
First, as shown in FIG. 1A, a copper diffusion barrier film 3, such as SiN deposited by plasma CVD, is formed on the lower layer interconnect line 1 including copper and the lower layer dielectric film 2. Then, an interlayer dielectric film 4 is formed on the copper diffusion barrier film 3. Although SiO2 deposited by plasma CVD is often used as the dielectric film 4, a low dielectric constant material is preferable for effective reduction of interconnect delay, as mentioned above. Here, the low dielectric constant material means a material having the dielectric constant less than that of SiO2, which is about 4.1 to 4.2, such as SiOC or SiOF films deposited by plasma CVD, or organic SOG (Spin on Glass), inorganic SOG or organic polymer film formed by coating method.
Next, an etching stopper 5 and an upper layer dielectric film 6 are formed on the dielectric film 4 in this order. For the etching stopper 5, a materials whose selectivity is larger than that of the upper layer dielectric film 6, such as SiN, SiC or SiO2, is selected. Besides SiO2, a low dielectric constant material can be also used for the upper layer dielectric film as well as the interlayer dielectric film 4.
Then, as shown in FIG. 1B, anisotropic etching is performed with the first resist pattern 7, used as a mask, which is formed with holes, and a via hole 7A is formed. After stripping the first resist pattern, anisotropic etching is performed with the second resist pattern 8, used as a mask, which is formed with trenches, and the upper layer interconnect trench 8A is formed as shown in FIG. 1C. In this process, etching stopper 5 serves to prevent the interlayer dielectric film 4 from being removed by etching.
Then, as shown in FIG. 1D, the inside walls of the via hole 7A and the upper layer interconnect trench 8A, are coated with barrier metal 9, and filled with interconnect metal 10 such as copper. The barrier metal 9 serves as a diffusion barrier against copper diffusion, and improvement of adhesiveness with the dielectric films and so on. As the barrier metal 9, a material having a high melting point, such as Ta, Ti or nitride which is deposited by PVD, is generally used. Since copper is formed on the upper layer dielectric film 6 with filling the via hole 7A and the upper layer interconnect trench 8A (no figure), CMP (Chemical Mechanical Polishing) is performed to form a via plug 7B and the upper layer interconnect line 8B.
In the interconnect formation by damascene process mentioned above, the etching stopper 5 prevents over-etching which induces the distortion of the via hole 7A, and as a result, it plays an important role for a high reliability, since the sizes of the via hole 7A and the upper layer interconnect trench 8A become uniform, regardless of the layout and the density.
However, the etching stopper mentioned above has a relatively large dielectric constant. For example, SiN which is a typical material for the etching stopper has a dielectric constant of 7. Therefore, even when a low dielectric constant material is used as a dielectric film, the reduction effect of electric capacitance among interconnect lines is inhibited by the etching stopper formed in a dielectric film. Some solutions have been developed to solve the problem of the etching stopper, such as making it thinner or changing the material of which to a lower dielectric constant material. However, they have not come to a practical use since there are many problems from the viewpoint of the productivity and the reliability.